Ke Wang

Ph.D. Student
Computer Engineering
George Washington University

About Me

I am a Ph.D. student in computer engineering at George Washington University, working with Prof. Ahmed Louri. My research interests are in the areas of computer architecture and parallel computing, with emphasis on on-chip interconnects and machine-learning-aided computer architecture designs. I received M.S. in Electronic and Computer Engineering from Worcester Polytechnic Institute in 2015 and B.S. in Electronics Engineering & Computer Science from Peking University, China in 2013.

I am about to graduate in Spring 2021 and currently on the job market, looking for research position. Please feel free to contact me!

Education

2015 – 2020

2013 – 2015

2009 – 2013

  • Ph.D. in Computer Engineering, George Washington University, Washington, DC
  • M.Sc. in Electronic and Computer Engineering,  Worcester Polytechnic Institute,Worcester, MA
  • B.Sc. in Electronics Engineering & Computer Science, Peking University, China

Research

Publications

  1. [ISCA '19] Ke Wang, Ahmed Louri, Avinash Karanth, and Razvan Bunescu ,  “IntelliNoC: a holistic design framework for energy-efficient and reliable on-chip communication for manycores”. Proceedings of the 46th International Symposium on Computer Architecture(ISCA’19). Phoenix, AZ, June 2019, pp. 589–600.
  2. [DATE '19] Ke Wang, Ahmed Louri, Avinash Karanth, and Razvan Bunescu . “High-performance, Energy-efficient, Fault-tolerant Network-on-Chip Design Using Reinforcement Learning”. Proceedings of 2019 Design, Automation & Test in Europe Conference & Exhibition(DATE’19). IEEE. Florence, Italy, Mar. 2019, pp. 1166–1171. (Nominated for Best Paper Award)
  3. [TPDS '20] Ke Wang and Ahmed Louri. “CURE: A High-Performance, Low-Power, and Reliable Network-on-Chip Design Using Reinforcement Learning”. IEEE Transactions on Parallel and Distributed Systems (2020), pp. 2125–2138. DOI:10.1109/TPDS.2020.2986297.
  4. [DAC '20] Hao Zheng, Ke Wang, and Ahmed Louri. “A Versatile and Flexible Chiplet-based System Design for Heterogeneous Manycore Architectures”. Proceedings of the 57th Annual Design Automation Conference(DAC’20). San Francisco, CA, July 2020. (Nominated for Best Paper Award)
  5. [IEEE MICRO '20] Ke Wang, Hao Zheng, and Ahmed Louri. “TSA-NoC: Learning-Based Threat Detection and Mitigation for Secure Network-On-Chip Architecture”. IEEE Micro: Special Issue on Machine Learning for Systems (2020). DOI:10.1109/MM.2020.3003576.
  6. [HPCA '21] Hao Zheng, Ke Wang, and Ahmed Louri. “Adapt-NoC: A Flexible Network-on-Chip Design for Heterogeneous Manycore Architectures”. to appear in Proceedings of the 27th IEEE International Symposium on High-Performance Computer Architecture (HPCA’21). IEEE. Seoul, South Korea, Feb. 2021.

Patents

  1. Ke Wang, Hao Zheng, and Ahmed Louri. Learning-Based High-Performance, Energy-Efficient, and Secure Interconnection Design Framework. U.S.Patent provisional application No. 63/019, 720, Filed May 5, 2020
  2. Hao Zheng, Ke Wang, and Ahmed Louri. A Versatile and Flexible Interconnection Network Design forChiplet-Based Manycore Architecture. Filed May 5, 2020, U.S.Patent provisional application No. No. 63/019, 670,Non–provisional application filed on October, 2020.
  3. Ke Wang and Ahmed Louri. Learning-Based High-Performance, Energy-Efficient, Fault-Tolerant On-Chip Communication Design Framework. U.S.Patent non–provisional application No. 16/547, 297, Filed Aug 21, 2019, 
  4. Ke Wang and Ahmed Louri. A Machine Learning-Based, High-Performance, Energy-Efficient, and Reliable Network-on-Chip Design. U.S.Patent provisional application No. 62/853, 455, Filed May 28, 2019

Professional Services

  • Program Committee
    IEEE S&P 2021(Shadow PC)
  • Journal Reviewer
    IEEE Transactions on Emerging Topics in Computing (TETC)
  • Conference Reviewer (Sub-reviewer)
    NoCs 2017~2019; ICCD 2018; HPCA 2018~2020;

Awards & Honors

  • Best Paper Candidate
    57th Design Automation Conference (DAC'20), San Francisco, CA, July 2020.
  • Best Paper Candidate
    Design, Automation & Test in Europe Conference & Exhibition (DATE’19). Florence, Italy, 2019
  • NSF GW I-Corps Site Grant Award
    George Washington University, Washington, D. C., 2019
  • Excellent Bachelor Dissertation Award
    School of Electronics Engineering and ComputerScience, Peking University, China, 2013

Contact Me

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